Non-volatile memory devices that comprise analog memory cells, such as Flash devices, are typically required to withstand electrical power supply interruptions. Various techniques are known in the art for protecting data stored in memory devices against power interruptions.
For example, U.S. Patent Application Publication 2007/0143531, whose disclosure is incorporated herein by reference, describes a method for power loss recovery for bit alterable memory. A bit alterable memory device includes status bits for a colony of memory cells. The state of each status bit may be changed depending on the programming state of the non-volatile bit alterable memory. The status bits are examined to determine the write status of two separate colonies of memory cells in the event of a power loss. The information gathered from the status bits is used by a power loss recovery mechanism to determine whether the data written to a plurality of memory cell colonies is partially written.
U.S. Pat. No. 6,988,175, whose disclosure is incorporated herein by reference, describes a method for managing page-based data storage media such as Flash media. New data are written to the storage medium in a manner that precludes corruption of old data if the writing of the new data is interrupted. Specifically, risk zones are defined by identifying, for each page, the other pages whose data are put at risk of corruption if writing to the page is interrupted. A page, which otherwise would be the target of a write operation, is not written if any of the pages in its risk zone contain data that could be corrupted if the write operation is interrupted.
U.S. Pat. No. 7,420,847, whose disclosure is incorporated herein by reference, describes a non-volatile memory device that is able to recover data in the event of a program failure without having to maintain a copy of the data until the write is completed. In some embodiments, the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data.
U.S. Pat. No. 7,924,613, whose disclosure is incorporated herein by reference, describes a method for data storage includes storing first data in analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data. Second data is stored in the analog memory cells in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data. The first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.
U.S. 2012/0005558, whose disclosure is incorporated herein by reference, describes a system and method for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.
U.S. 2010/0217920, whose disclosure is incorporated herein by reference, describes a memory system that includes a Flash memory and a memory controller. The Flash memory has at least two addresses with different program times. The memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the Flash memory. The assigned address is used to store data of the memory controller in the Flash memory.